Argo Semiconductors  can provide assistance and design services in the following areas:

Standards:  WLAN IEEE802.11a/n, WiMAX SC IEEE802.16a, Bluetooth BDR/EDR, 5G/LTE/GSM/EDGE, NFC

Architectures: Heterodyne, low IF, direct down-conversion, direct modulation, polar, direct transmission


Analog IC: RF transceiver, RF Analog Front-End, PLL, linearized LTI/LTV components

Analog/RF impairment modeling: Channel, IQ mismatch, PLL impairments (CP, VCO, spur, phase noise), PA non-linearity, line delays, antenna mismatch, R/C component inaccuracy, ADC/DAC non-linearity, sampling jitter

Analog Design Services

Design Specification and Architecture Definition

  • Radio specification extraction from the overall system specification both at high level (interfaces,  datapath requirements) and per block (Tx path, RX path, PLL)

Development phase

  • Radio specification translation to Block level specs, including verilog-A models, where applicable
  • IC Block design & verification (e.g. LNA, mixer)
  • Detailed modeling (S-parameters/ lumped) of inductors and critical metal layers using EM tools (Momentum / EMX)
  • Highlight: 5G mmWave transceiver, 5G mmWave AFE and antenna array

IC Layout

  • Floor plan of the radio layout; IC block layout; Full radio layout and GDS file
  • Reliability checks (Overvoltage, Electromigration, Aging)
  • Top level verification; Layout verification (DRC, LVS, ERC, ANT); Simulated performance of the extracted layout; Inclusion of detailed package/pcb models

Validation testing; Test plans generation; functional block testing

Digital Design Services

Integrated environment for modeling mixed analog-digital systems

  • Matlab/Simulink, Simulink-Cadence co-simulation, simRF

Applicable to any hybrid system including communincations systems

  • Modem DSP, analog/RF, channel, PLL, ADC/DAC, power amplifier

Fixed-step time-discrete modeling of analog and mixed signal components (PLL, OpAmp, ΔΣ-ADC, synchronization logic)

Fast simulation:  (can auto-generate and run the C equivalent of the block level model)

Short development cycle, reliable update cycles: (automated RTL code generation for the digital circuitry)

Feature verification: uniformly applied on digital blocks, analog blocks and system level

Functional verification: (code coverage using the Simulink-RTL co-simulation environment)